The production of semiconductor devices, such as LEDs, lasers, or transistors, is a complex procedure. The semiconductor value chain starts with the substrate and continues through front-end production, where epitaxy represents the first and most value-creating process step. This is followed by wafer processing steps such as lithography and plasma etching, and finally by back-end processes including die separation and device packaging. LayTec’s metrology is designed for front-end production on wafer level. In various steps of the value chain, LayTec metrology tools measure the wafer: in-situ during epitaxy, post-epi wafer mapping and in-situ during plasma etching and save data in a unified LayTec SQL database, creating the LayTec metrology ecosystem. Linked by the wafer ID, the data measured on the same wafer in different process steps is combined and the overall amount of information on the wafer increases. This provides prior knowledge from upstream processes that facilitate the analysis of downstream processes – a principle we call Connected Metrology^®, providing additional value far beyond the individual measurements.

From the in-situ metrology during the epi process, the number of layers, the position of interfaces and the layer thickness as well as ternary composition information is known for a specific wafer – being more precise than just the nominal layer stack from the growth recipe and taking run-to-run and wafer-to-wafer variations into account. Post epi wafer mapping adds precise uniformity information about layer thickness and composition. While the stand-alone analysis of a complex multi-layer stack can be limited in precision, the connected metrology approach allows the use of the layer thickness information from the epi as starting values for the 2D mapping analysis. Vice versa, uniformity results can be used to improve uniformity of the epi process and helps to establish run-to-run control.

When etching back into the layer stack, it is crucial to stop the etching at exactly the right depth of the layer stack. Automated and precise end-pointing is the goal. As this needs to happen in real-time, additional information about the specific wafer is of high value. With the knowledge of the exact layer thickness for each layer in the stack from the upstream measurements, this challenge is substantially eased by using Connected Metrology again. The in-situ data of the epi process, plotted time-inverted, already provide a useful target trace for the etching process. With a full simulation and parametrization of the in-situ reflectance data, re-modelled for the lower temperature of the etching process and with matching etch rates, a very precise forecast of the in-situ data during the plasma etching process is available.  Possible non-uniformities of the epi process provided by the mapping tool or a known non-uniformity of the etching process can be taken into account, when designing the end-pointing algorithm, so that the in-spec area of the wafer can be maximized.      

Connected Metrology^® transforms individual measurements into a coherent, wafer-centric data foundation, enabling superior process control and safeguarding the value of epitaxial wafers throughout front-end manufacturing.